(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making more reliable self-aligned source/drain contacts for field effect transistors (FETs). A double-spacer technology is used in which second sidewall spacers are used to prevent damage to the first sidewall spacers thereby improving the electrical isolation between the self-aligned source/drain contacts and the polysilicon FET gate electrodes.
(2) Description of the Prior Art
One type of semiconductor device most commonly used for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET). These FET devices are fabricated by forming a polysilicon gate electrode having self-aligned source/drain contact (SAC) areas adjacent to the gate electrode, and are referred to as SAC-FETs. These SAC-FETs are preferred because of their small size, high packing density, low power consumption, and low manufacturing cost.
Conventional SAC-FETs are typically fabricated by patterning a stacked gate electrode layer comprised of a polysilicon layer and a silicon oxide (SiO.sub.2) cap layer over a thin gate oxide on the device areas of a single crystal semiconductor substrate. The gate electrode structure is itself used as an implant barrier mask to form self-aligned lightly doped source/drain areas (LDD areas) in the substrate adjacent to the sides of the gate electrode. Insulating sidewall spacers, usually composed of SiO.sub.2, are formed next and serve to mask the LDD areas, while the heavily doped source/drain contact areas are formed by ion implantation or at a later processing step by solid state diffusion form a doped polysilicon layer.
Unfortunately, several processing problems arise when these closely spaced SAC-FETs having sub-half-micrometer dimensions are fabricated. One problem occurs because much thinner SiO.sub.2 sidewall spacers are used to achieve the higher device density. When the self-aligned contacts are etched in the overlying insulating layer to the source/drain areas, and a cleaning step is used to remove any remaining native oxide on the substrate, the thin oxide sidewall spacer is attacked resulting in electrical shorts between the SAC and FET gate electrode.
Several methods for making improved SAC-FETs have been reported in the literature. Matsumoto et al. in U.S. Pat. No. 5,668,052 teach a method for making improved self-aligned contacts (SAC) that avoids electrical shorts by using a second sidewall spacer formed from a silicon nitride etching stopper film. However, a reflection prevention film (anti-reflection coating) is used under the photoresist layer and is etched at the same time the silicon nitride sidewall spacers are formed. Matsumoto requires that the reflection prevention film and the etching stopper film be relatively thick and about equal in thickness. This limits the minimum spacing that can be achieved between closely spaced SAC-FETS. Also reported in the prior art of Matsumoto is a method in which a silicon nitride second sidewall spacer is used without an anti reflecting layer. However, neither Matsumoto or the prior art addresses the concurrent formation of the gate electrode contact that reduces process steps. Fukase et al. in U.S. Pat. No. 5,208,472 teach a method of using a silicon rich oxide (SRO) layer as a second sidewall spacer to prevent shorts between the SAC and the gate electrode, and also teach the concurrent formation of a contact to the FET gate electrode. However, Fukase requires an additional masking and etch step. Another method of forming SAC-FETs is described by Hsue, U.S. Pat. No. 5,378,654, in which a single sidewall spacer is used. Su in U.S. Pat. No. 5,208,472 describes a method in which a dielectric layer is deposited and is anisotropically plasma etched to form a second sidewall spacer that reduces leakage current between source/drain and gate electrode. Ho in U.S. Pat. No. 5,364,804 describes a method for forming first sidewall spacers by thermal oxidation and then uses a second silicon nitride sidewall spacer to provide a better, more vertical sidewall for improved metal step coverage. Nguyen in U.S. Pat. No. 5,439,846 describes a method for forming a silicon nitride first sidewall spacer as an etch-stop layer on a gate electrode when etching self-aligned contact openings in an overlaying BPSG and an undoped silicon oxide glass. Chin et al., U.S. Pat. No. 5,106,783, describe a method for forming a bipolar transistor in which polysilicon emitter contacts are formed having oxide sidewalls. A second polysilicon layer is deposited and etched back to form self-aligned base contacts.
Therefore, there is still a strong need in the semiconductor industry to provide self-aligned contacts with improved electrical isolation between contacts and gate electrodes while reducing the number of process masking steps.